The present invention relates to the design of integrated circuits (ICs), and more specifically, to statistical timing analysis of such circuits.
Generally, ICs have data signals and a clock; the data signal needs to reach a certain node at the correct time vis-a-vis the time when the corresponding clock cycles the device at that node. If the data signal does not arrive in time, the clock is too fast, or alternatively, the data signal is taking too long to propagate (path is too slow). Classically, this problem was dealt with by looking at a worst case or process corner scenario wherein the logic gates have the worst possible combination of delays, and ensuring functioning under such conditions.
As ICs move to smaller-scale technology, this classic approach has proven to be excessively pessimistic. Accordingly, statistical techniques are now being used. In such techniques, delay is treated as a random variable and variations, such as process variations, are treated as following a Gaussian error curve. In this statistical approach, it can be decided, for example, what percentage yield is desirable for a given chip design.